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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:25:17 04/16/2012 
-- Design Name: 
-- Module Name:    video_logic_unit - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vga_timing_controller is
	Port (
		clk : in std_logic;
		h_sync : out std_logic;
		v_sync : out std_logic;
		should_blank : out std_logic;
		h_count : out natural range 0 to 639;
		v_count : out natural range 0 to 479
	);
end vga_timing_controller;

architecture Behavioral of vga_timing_controller is

begin
	
	-- For implementation details, see
	-- /docs/nexys2_rm.pdf	

	h_sync <= '0';
	v_sync <= '0';
	should_blank <= '0';
	
	h_count <= 0;
	v_count <= 0;
	
end Behavioral;
